The Alpha processor from the Digital Equipment Corporation (DEC) is the first
non-Intel-based processor on which Linux was commercially available and is
substantially different from its Intel cousins. The most significant difference
is that the Alpha AXP is a Reduced Instruction Set Computer
(RISC), as compared to
the Intel, which is a Complex Instruction Set Computer (CISC).
this book into a textbook on microprocessor design, I can simply say that the
difference is that RISC has fewer instructions (the instruction set is reduced)
and therefore takes more instructions to do a specific job. A CISC processor has
more instructions and takes fewer instructions to do the same job.
Imagine someone told you to stand up and open the door.
The CISC instruction
might simply say, "Go open the door." Using what's built into your
CPU (your brain), you know to translate this to "stand up
and open the door." On the other hand, the RISC instructions
might be "Stand up. Turn left and take two paces forward. Turn right, and take
three paces forward.
Raise right hand, etc." There might then be a CISC instruction
that says, "Go open the window." However, the RISC instructions
might be "Stand up. Turn left, and take two paces forward. Turn left, and take three
paces forward, etc."
Not only does the CISC give fewer instructions, it also
requires less logic
circuitry. As a result, an Alpha AXP processor can run at higher speeds than an
Intel. This does not make the Alpha AXP intrinsically faster! Take our
example. I simply tell you to open the window, and you do it. However, giving
you each instruction individually takes more time. One significant difference is
that when the PentiumPro just broke the 200Mhz barrier, the Alphas
were more than twice that.
Even if the increase in clock speed is not considered, the design of the
Alpha AXP enables it to do more work per cycle. Several issues were addressed to
help eliminate any aspect of the processor that would hinder multiple
instruction issues. For example, there are no branch delay or skip instructions.
As a result of its design, the Alpha AXP (as of this writing) can get up to 10 new
instructions per cycle.
In addition, the Alpha AXP was designed to run with multiple processors, though
that's not to say that it can't run as a single processor. The Alpha AXP was
designed with several instructions that simplify adding multiple processors.
Unlike other processors, this functionality was designed from the beginning and
didn't have to be built onto an existing system.
One advantage of Alpha AXP is that it doesn't have a lot of baggage to carry
around. The Intel 80x86 family is based on the 8086 and is completely
backward-compatible. If you have an 8086 program, it will run on an PentiumPro.
The Alpha AXP was developed with a full 64-bit architecture, although it has a few
32-bit operations for backward compatibility.
Part of the 64-bit architecture is the Alphas 64-bit virtual
address space. All values (registers, addresses, integers,
etc.) are operated on as full 64-bit quantities. Unlike with the Intel
processors, there are no segmented addresses. In some cases, the
operating system may restrict the number of bits that is
used to translate the virtual address; however, at least 43 bits are used.
Like the Intel, Alphas memory protection is done on a per-page basis. The
design of the paging mechanism in Intel specifies a 4KB
page, but the Alpha AXP can have 8KB, 16KB, 32KB, or even 64KB pages. In addition,
the Alpha AXP also uses many-to-one page mapping, as does the Intel, so that
multiple processors can have a virtual memory
address that references the same page in physical
The Alpha AXP architecture is a 64-bit load/store RISC architecture
designed with speed in mind.
All registers are 64 bits in length; 32 integer registers and 32
floating point registers.
Integer register 31 and floating point register 31 are
used for null operations. A read from them generates a zero value and
a write to them has no effect.
All instructions are 32 bits long and memory operations are either reads
The architecture allows different implementations so long as the
implementations follow the architecture.
There are no instructions that operate directly on values stored in
memory; all data manipulation is done between registers.
So, if you want to increment a counter in memory, you first read it
into a register, then modify it and write it out.
The instructions only interact with each other by one instruction
writing to a register or memory location and another register reading
that register or memory location.
One interesting feature of Alpha AXP is that there are instructions
that can generate flags, such as testing if two registers are equal,
the result is not stored in a processor status register, but is instead
stored in a third register. This may seem strange at first, but removing this
dependency from a status register means that it is much easier to build a
can issue multiple instructions every cycle.
Instructions on unrelated registers do not have to wait for each other
to execute as they would if there were a single status register.
The lack of direct operations on memory and the large number of registers
also help issue multiple instructions.
The Alpha AXP architecture uses a set of subroutines, called privileged
architecture library code (PALcode).
PALcode is specific to the operating system, the CPU implementation
of the Alpha AXP architecture and to the system hardware.
These subroutines provide operating system primitives for context
switching, interrupts, exceptions and memory management.
These subroutines can be invoked by hardware or by CALL_PAL
PALcode is written in standard Alpha AXP assembler with some
implementation specific extensions to provide direct access to low
level hardware functions, for example internal processor registers.
PALcode is executed in PALmode, a privileged mode that stops some
system events happening and allows the PALcode complete control of
the physical system hardware.